How to design an active rectifier - schematic

In this tutorial, we are going to design an active rectifier in CMOS 180 nm, including the design of the schematic and layout considerations.

Schematic Design

This rectifier consists of three main components, as shown in Fig. 1:

1. Cross-coupled PMOS transistors: These transistors serve as switches to transform the sine wave input into a steady voltage output by charging the load capacitor (CL).
2. Active diodes with common-gate comparators and buffers: Using comparators, these active diodes detect the point where the input voltage crosses zero. This information is then used to control the on/off state of the NMOS transistors.
3. Self bulk bias (BB): To ensure the PMOS transistors are optimally biased, a self bulk bias mechanism is employed. This helps determine the highest voltage from the input and rectified voltage.

By employing cross-coupled PMOS transistors as switches, the rectifier stabilizes the input sine wave, charging the load capacitor (CL) for a constant voltage output. The active diodes, aided by comparators and buffers, detect zero crossings in the input voltage, enabling control over the NMOS transistor switching. This design outperforms diode-connected NMOS setups, yielding a higher voltage conversion ratio (VCR). To ensure proper biasing for the PMOS transistors, the self bulk bias (BB) mechanism identifies the peak voltage from both input and rectified sources.

Common-Gate Comparator

The two comparators CMP1 and CMP2 are common-gate push-pulldifferential-input comparators, with the bias currents provided by M₇and M₈. As described above, when V_AC2– V_AC1> |V_thp|, M_P2 is turned on, and V+ keeps going down.When V_AC1 swings below 0 V, M₁ of CMP1 sinks a largercurrent than M₂ does. As M₄ is diode-connected,therefore, V_G4 drops with V+, and reduces V_GS3. Thecurrent of M₁ is mirrored to M₆ through M_5, causingM₆ to source a larger current than M₃ can sink, thusdriving V_rect as well as V_GN1 high and turns on theactive-diode switch M_N1. In the other half cycle, V+ goes up and V-goes down, then M_N2 will be turned on in a similar manner andconducts current from ground to V_rect through the AC source.

Take I_M7=I₁ and I_M8=I₂,I_M5=I₃, I_M6=I_4,1 and I_M3=I_4,2,V_G4=V₁ and V_G2=V₂. I₁, I₂are assumed constant, so V₂ and V_GS4 will be constant.

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Simulation Results

In this section, we delve into the simulation outcomes and the impact of various parameters on both power conversion efficiency (PCE) and voltage conversion ratio (VCR). For instance, Figure 2 provides insight into the rectifier's behavior through a transient simulation spanning 5 microseconds. As depicted, it requires close to 1 microsecond to attain a stable state. Additionally, the graph reveals the gate voltage trends of the active diodes. Notably, these diodes activate precisely when the input voltage (Vin) intersects the zero-crossing point.

Moreover, Figure 3 displays the current usage during switching, covering both NMOS and PMOS transistors, along with comparator consumption. The main reason for power loss, leading to lower power conversion efficiency (PCE), is the delay in activating the switching active diodes. This delay results in reverse current leakage within the rectifier. To tackle this, a potential solution is to improve the comparator's design. This enhancement can effectively address the issue, leading to better overall performance of the rectifier.

Transistor Sizing Effect on PCE and VCR

In this part, we will explore how adjusting the size of the power MOSFETs (3.3V IO CMOS) impacts the voltage conversion ratio (VCR) and power conversion efficiency (PCE). Figure 4 illustrates the influence of NMOS (M_N1,2) width on PCE and VCR, while Figure 5 demonstrates a similar impact for PMOS (M_P1.2) width. On the other hand, when aiming to conserve space, it's advisable to opt for the smallest feasible transistor sizes. For example, for NMOS and PMOS widths, values like 0.6 mm and 16 mm could be considered suitable choices.