How to design an active rectifier - layout

In this section, we'll delve into how to design the layout for the active rectifier. A key consideration here is to aim for symmetry in the layout. This helps to reduce mismatches and errors caused by process variations in the manufacturing.

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Common-Gate Comparator

Let's take a look at the layout of the Common-Gate Comparator in Figure 1. In this layout, we've used 3.3 V IO MOSFETs to ensure that the rectifier functions well even at higher voltages. To keep things smooth and prevent potential issues like excess noise and latch-up effects, we've placed the transistors within protective rings made of P and N-type materials. This layout choice is aimed at ensuring the rectifier operates reliably and consistently.

Active Rectifier

Figure 2 illustrates the symmetrical layout of the proposed active rectifier. In this design, the PMOS transistors take up the most space on the layout, followed by the NMOS transistors.