OTA Design in every CMOS technology

December 20, 2023
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To start on the design of an amplifier, it's essential to establish a set of parameters as a starting point. In this discussion, our objective is to design a one-stage Operational Transconductance Amplifier (OTA) while working within the constraints of 180nm (or 40 nm) CMOS technology. This technology stipulates certain limitations and characteristics for our amplifier. Here are the key specifications we aim to achieve:

  • Gain: a minimum gain of greater than 40 dB.
  • Gain-Bandwidth Product (GBW): The desired GBW is 2.5 MHz, indicating that we want our amplifier to maintain a high gain over a wide range of frequencies.
  • Slew Rate (SR): The amplifier should exhibit a slew rate of 2 V/μs, which is crucial for handling rapid changes in the input signal.
  • Load Capacitance (CL): Our design should be capable of driving a load capacitance of 10 pF, ensuring it can interface with external components effectively.
  • VDS,sat: The minimum drain-source voltage (VDS,sat) for the transistors we'll be using is 0.155 V.
  • Transistor Length: We'll begin with a minimum transistor length of 0.72 μm (4L minimum), as per the constraints of the 180nm CMOS technology.

Now, let's delve into the intricacies of designing an amplifier with these specifications:

Gain:40 dB=100

GBW:2.5 MHz → GBW=gm /(2π CL) ⇒ gm=0.157 mmho

S.R=Iss /CL  ⇒Iss=20 μA

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Design the NMOS Bias Transistor:

We have calculated a desired transconductance (gm) of 0.157 mS (millisiemens) and a current of 10 μA for the NMOS bias transistor.To find the width (W) required for the NMOS transistor, We need to simulate and sweep width of the following transistor at 10 uA, and find the width related to gm=0.157 mmho. Consequently, we reach the width of 7.5 μm for NMOSs.

Size the PMOS Transistor:

To maintain roughly the same gate-source voltage for the PMOS transistor, which is typically complementary to the NMOS transistor in biasing circuits, it should also have a width of 15 μm.

Calculate Bias Voltage and Current:

‍The bias voltage at the gate of the NMOS transistors should be 0.545+0.155=0.7. The total bias current (Iss) for the circuit should be 20 μA.

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And the final OTA schematic is: